Electronic devices, to be serviceable under a wide variety of environmental conditions, must be able to withstand moisture, heat, and abrasion resistance, among other stresses. A significant amount of work has been reported directed toward the preparation of coatings for electronic devices which can increase the reliability of the devices. None of the conventional coatings available today, including ceramic and metal packaging, can perform well enough by itself to protect an electronic device against all environmental stresses.
A common cause of failure of electronic devices is microcracks or voids in the surface passivation of the semiconductor chip allowing the introduction of impurities. Thus a need exists for a method which will overcome the formation of microcracks, voids or pinholes in inorganic coatings of electronic devices.
Passivating coatings on electronic devices can provide barriers against ionic impurities, such as chloride ion (C1-) and sodium ion (Na+), which can enter an electronic device and disrupt the transmission of electronic signals. The passivating coating can also be applied to electronic devices to provide some protection against moisture and volatile organic chemicals.
Amorphous silicon (hereinafter a-Si) films have been the subject of intense research for various applications in electronic industries, however, the use of a-Si films for environmental or hermetic protection of electronic devices is unknown. A number of possible processes have been previously disclosed for forming a-Si films. For instance, for producing films of amorphous silicon, the following deposition processes have been used: chemical vapor deposition (CVD), plasma enhanced CVD, reactive sputtering, ion plating and photo-CVD, etc. Generally, the plasma enhanced CVD process is industrialized and widely used for depositing a-Si films.
Known to those skilled in the art is the utility of substrate planarization as an interlayer within the body of an electronic device and between the metallization layers. Gupta and Chin (Microelectronics Processing, Chapter 22, "Characteristics of Spin-On Glass Films as a Planarizing Dielectric", pp349-65, American Chemical Society, 1986) have shown multilevel interconnect systems with isolation of metallization levels by conventional interlevel dielectric insulator layers of doped or undoped SiO.sub.2 glass films. However, CVD dielectric films provide only at best a conformal coverage of substrate features which is not conducive to continuous and uniform step coverage by an overlying metallization layer. The poor step coverage results in discontinuous and thin spots in the conductor lines causing degradation of metallization yields as well as device reliability problems. Spin-on glass films have been utilized to provide interlayer isolation between the metallization layers, the top layer of which is later patterned by lithographic techniques. Topcoat planarization on the surface of an electronic device as opposed to planarizing interlevel dielectric layers, however, is unknown.
Under the teachings of the prior art, a single material most often will not suffice to meet the ever increasing demands of specialty coating applications, such as those found in the electronics industry. Several coating properties such as microhardness, moisture resistance ion barrier adhesion, ductility, tensile strength, thermal expansion coefficients, etc., need to be provided by successive layers of different coatings.
Silicon and nitrogen-containing preceramic polymers such as silazanes have been disclosed in various patents, including U.S. Pat. No. 4,404,153, issued Sept. 13, 1983 to Gaul, wherein there is disclosed a process for preparing R'.sub.3 SiNH- containing silazane polymers by contacting and reacting chlorine-containing disilanes with R'.sub.3 Si).sub.2 NH where R' is vinyl, hydrogen, an alkyl radical of 1 to 3 carbon atoms or the phenyl group. Gaul also teaches therein the use of the preceramic silazane polymers to produce silicon-carbon-nitrogen-containing ceramic materials.
Gaul in U.S. Pat. No. 4,312,970, issued Jan. 26, 1982, obtained ceramic materials by the pyrolysis of preceramic silazane polymers, which polymers were prepared by reacting organochlorosilanes and disilazanes.
Gaul in U.S. Pat. No. 4,340,619, issued July 20, 1982, obtained ceramic materials by the pyrolysis of preceramic silazane polymers, which polymers were prepared by reacting chlorine-containing disilanes and disilazanes.
Cannady in U.S. Pat. No. 4,540,803, issued Sept. 10, 1985, obtained ceramic materials by the pyrolysis of preceramic silazane polymers, which polymers were prepared by reacting trichlorosilane and disilazanes.
Dietz et al., U.S. Pat. No. 3,859,126, issued Jan. 7, 1975, teaches the formation of a composition comprising PbO, B.sub.2 O.sub.3, and ZnO, with optional various oxides including SiO.sub.2.
Rust et al., U.S. Pat. No. 3,061,587, issued Oct. 30, 1963, teaches a process for forming ordered organo silicon-aluminum oxide copolymers by reacting dialkyl diacyloxysilane or dialkyl dialkoxysilane, with trialkylsiloxy dialkoxy aluminum.
Glasser et al. ("Effect Of The H.sub.2 O/TEOS Ratio Upon The Preparation And Nitridation Of Silica Sol/Gel Films", Journal of Non-Crystalline Solids 63, (1984) p.209-221) utilized tetraethoxysilane without additional metal oxides to produce films for subsequent high temperature nitridation.
The instant invention relates to the enhancement of the protection of electronic devices by the low temperature formation of thin multilayer ceramic or ceramic-like coatings on the surface of the device. What has been discovered is a method of forming coatings from a silicate ester and one or more metal oxides, which are subsequently coated with one or more silicon, or silicon and nitrogen, or silicon and carbon and nitrogen-containing, ceramic or ceramic-like coatings,